搜索资源列表
verilog_sdram_controller_testbench
- SDRAM 控制器 ，Verilog版本的，带有完整的SDRAM 仿真模型，testbench等，能够实际使用，并且利于学习-The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz
Camera_Interface_Verilog
- 该源代码包是基于片上系统的摄像头接口的Verilog语言程序，它包括以下5部分：RTL源代码，测试平台，软件仿真C代码，FPGA综合时的sdc和ucf文件，说明文档。-This source code package is the camera interface module based on the SoC use Verilog language. It has the following 5 parts: RTL code, testbench, software simulating
vga
- VGA驱动及显示程序，用Verilog编写代码实现VGA的驱动和显示，并且提供了测试程序Testbench通过测试能得到正确的时序波形。-the source code for driving VGA and displaying the images,the testbench was offered.
counter60
- Verilog语言编写的模60计数器和testbench-Verilog language model 60 counters and testbench
Writing_Efficient_Testbenches
- vhdl语言 和verilog hdl语言的测试程序编写- testbench for vhdl and verilog
i2c.tar
- 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
santhosh_multiplier
- This has verilog code for multiplication.. It will be useful for beginners of verilog.. The testbench for multiplier is also attached with the file setup. Comments are welcome
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
cpu8088
- 8088 verilog 源代码，详见V代码以及TESTBENCH仿真
vani_tut
- A total of 52 files showing examples of shell scr ipting for Cadence NCSIM simulator, multiple single module + testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Dist
i2c-IPcore
- i2c的完整可用的Verilog代码，包含testbench.-i2c complete Verilog code is available, including the testbench.
PCI_testbench
- 基于FPGA的PCI接口源代码及Testbench Verilog程序代码-PCI_verilog_with testbench.
rs232
- 异步串行传输的verilog hdl 功能文件以及测试文件-The verilog hdl source and the testbench of asynchronous serial transmission
SystemVerilogEventRegionsRaceAvoidanceGuidelines.r
- The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This pap
testbench_vantage
- 芯片设计验证测试技术方法，基于verilog语言-testbench for ASIC Design, Verilog
rs232
- RS232的串口控制器，本程序中的每个小模块都有与之对应的testbench，模块清晰，实现结构简单。很适合Verilog编程初学者来练习！-RS232 serial port controller, the program has a small module for each corresponding testbench, module definition, to achieve simple structure. Verilog programming is suitable for
I2C
- I2C总线接口的Verilog源码文件和modelsimd的测试文件-Verilog source code of I2C bus interface and testbench code of modelsim.
adder_4
- 详细介绍了四位加法器的verilog代码，还包括详细的testbench代码。-Details of the four adder verilog code, also includes detailed testbench code.
Verilog_testbench
- 介绍在FPGA广泛使用的Verilog语言以及如何编写高效的testbench，让仿真更加接近实际模型。-Introduction widely used in FPGA Verilog language and how to write effective testbench, so that a more realistic simulation model.